Semiconductor capacitor with diffusion prevention layer

ABSTRACT

There is provided the capacitor which has the lower electrode having a structure in which the first conductive layer containing a first metal, the second conductive layer that is formed on the first conductive layer and made of the metal oxide of the second metal different from the first metal, and the third conductive layer that is formed on the second conductive layer and made of the third metal different from the first metal are formed sequentially; the dielectric layer formed on the lower electrode; and the upper electrode formed on the capacitor dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority of JapanesePatent Applications No. 2002-16083, filed in Jan. 24, 2002, and No.2001-213547, filed in Jul. 13, 2001, the contents being incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a capacitor and a method ofmanufacturing the same and, more particularly, a capacitor having aferroelectric layer or a high-dielectric layer and a method ofmanufacturing the same.

[0004] 2. Description of the Prior Art

[0005] The high-dielectric layer such as the BST ((Ba,Sr)TiO₃) layer,the ST (SrTiO_(x)) layer, the Ta₂O₅ layer, etc. and the ferroelectriclayer such as the PZT (PbZr_(x)Ti_(1-x)O₃) layer, etc. are widely usedas the capacitor dielectric layer in DRAM (Dynamic Random AccessMemory), FeRAM (Ferroelectric Random Access Memory), etc. by employingpositively the high dielectric constant and the inverted polarizationcharacteristic.

[0006] Also, in the ferroelectric capacitor of FeRAM, the planar-typecapacitor having the structure in which the connection between the lowerelectrode of the capacitor and the impurity diffusion region of thetransistor is extracted from the upper side of the lower electrode ispractically used. In this case, the stacked-type capacitor having thestructure in which the lower electrode is connected to the impuritydiffusion region via the conductive plug formed immediately under thelower electrode is required in future to reduce the cell area.

[0007] If the high-dielectric oxide layer or the ferroelectric oxidelayer is used as the capacitor dielectric layer, platinum (Pt) is widelyused as the electrode material. This is because the conductivity of theplatinum is high, the platinum can withstand the high-temperatureprocess in the course of formation of the dielectric layer, the platinumcan control the orientation direction of the capacitor dielectric layerformed thereon, etc.

[0008] On the contrary, the platinum has the high oxygen permeability.Therefore, if the lower electrode made of the platinum is formed on theplug in the stacked-type capacitor, the oxygen can transmit through thelower electrode in the annealing process in the course of the formationof the capacitor dielectric layer to oxidize the plug. As a result, forexample, if the plug is formed of tungsten, the insulating tungstenoxide layer is formed between the plug and the lower electrode and thusthe contact between the plug and the lower electrode is lost.

[0009] Therefore, in the stacked-type capacitor, the stacked structuresuch as the Pt/Ir structure in which the Ir layer and the Pt layer areformed sequentially from the bottom, the Pt/IrO₂ structure in which theIrO₂ layer and the Pt layer are formed sequentially from the bottom, thePt/IrO₂/Ir structure in which the Ir layer, the IrO₂ layer, and the Ptlayer are formed sequentially from the bottom, or the like is employedas the lower electrode structure.

[0010] The iridium (Ir) layer and the iridium oxide (IrO₂) layer has thevery small oxygen permeability and acts as the oxygen barrier in theannealing process. Therefore, if this layer is formed as the underlyinglayer of the platinum layer serving as the lower electrode of thestacked-type capacitor, the oxidation of the plug under the lowerelectrode can be prevented in the course of the formation of thecapacitor dielectric layer.

[0011] For example, in Patent Application Publication (KOKAI) Hei9-22829, it is proposed to use the Pt/IrO₂/Ir structure as the lowerelectrode of the ferroelectric capacitor having the stacked structure.This structure succeeds in assuring the desired characteristic of theferroelectric layer, while suppressing the oxidation of the lower layerstructure of the capacitor by the annealing process in the oxygenatmosphere.

[0012] However, in the case that the PZT layer deposited by thesputtering method is applied as the capacitor dielectric layer, it isfound that, if the lower electrode structure containing theiridium-based oxygen barrier layer (Ir layer, IrO₂ layer) is employed,the increase in the leakage current of the capacitor is brought about.

[0013] If the PZT layer is deposited on the lower electrode by thesputtering, the as-deposited PZT layer is in the amorphous state and thehigh-temperature annealing process is needed to crystallize the PZTlayer.

[0014] However, if the high-temperature annealing process is applied tocrystallize the PZT layer after the amorphous PZT layer is deposited onthe lower electrode having the structure in which the Pt layer is formedon the iridium-based oxygen barrier layer, the iridium element in theiridium-based oxygen barrier layer transmits through the Pt layer todiffuse into the PZT layer and then is introduced into the PZT crystal.As a result, the insulating property of the PZT crystal is lowered.

[0015] Such phenomenon can be avoided by growing the PZT layer that isin the crystal state on the lower electrode or crystallizing the PZTcrystal at the low temperature. In this case, the dielectric constant ofthe formed PZT layer becomes small.

SUMMARY OF THE INVENTION

[0016] It is an object of the present invention to provide a capacitorcapable of preventing the oxidation of the conductive plug formedimmediately under the lower electrode and also preventing the metallicdiffusion from the lower electrode to the capacitor dielectric layer inthe course of the formation and the crystallization of the capacitordielectric layer, and a method of manufacturing the same.

[0017] The above subject can be overcome by providing a capacitor whichcomprises a lower electrode having a structure in which a firstconductive layer containing a first metal, a second conductive layerthat is formed on the first conductive layer and made of a metal oxideof a second metal different from the first metal, and a third conductivelayer that is formed on the second conductive layer and made of a thirdmetal different from the first metal are formed sequentially; adielectric layer formed on the lower electrode; and an upper electrodeformed on the capacitor dielectric layer.

[0018] In the above capacitor, the first metal is iridium, the metaloxide of the second metal is a metal oxide of a platinum group metalexcept the iridium, and the third metal is the platinum group metalexcept the iridium.

[0019] In the above capacitor, the second metal is a same element as thethird metal, and an interface conductive layer made of the second metalis further formed between the first conductive layer and the secondconductive layer.

[0020] The above subject can be overcome by providing a capacitormanufacturing method which comprises the steps of forming a firstconductive layer containing a first metal on an insulating layer;forming a second conductive layer made of a metal oxide of a secondmetal, that is different from the first metal, on the first conductivelayer; forming a third conductive layer made of a third metal, that isdifferent from the first metal, on the second conductive layer; forminga dielectric layer on a lower electrode; forming a fourth conductivelayer on the dielectric layer; patterning the first conductive layer,the second conductive layer, and the third conductive layer to form acapacitor lower electrode; patterning the dielectric layer to form acapacitor dielectric layer; and patterning the fourth conductive layerto form a capacitor upper electrode.

[0021] In the capacitor manufacturing method, the second metal is a sameelement as the third metal, and the capacitor manufacturing methodfurther comprises the step of forming an interface conductive layer madeof the second metal between the first conductive layer and the secondconductive layer.

[0022] According to the present invention, the capacitor is constructedby the lower electrode having the first conductive layer in which thefirst metal (e.g., iridium) is contained, the second conductive layerwhich is formed on the first conductive layer and made of the metaloxide of the second metal (e.g., the platinum group except the iridium),and the third conductive layer which is formed on the second conductivelayer and made of the third metal (e.g., the metal of the platinum groupexcept the iridium), the capacitor dielectric layer formed on the lowerelectrode, and the upper electrode formed on the capacitor dielectriclayer.

[0023] According to the structure of such lower electrode, the diffusionof the oxygen into the conductive plug formed immediately under thelower electrode in the course of the layer formation of the capacitordielectric layer can be prevented by the first conductive layer, andalso the diffusion of the first metal from the first conductive layer tothe capacitor dielectric layer can be prevented by the second conductivelayer.

[0024] Therefore, the electric connection between the conductive plugand the lower electrode can be improved, and also the sufficientcrystallization of the capacitor dielectric layer can be achieved whilepreventing the diffusion of the first metal into the dielectric layerafter the dielectric layer is formed on the lower electrode. As aresult, the high performance capacitor having the desired electriccharacteristics can be manufactured.

[0025] In addition, according to the present invention, the interfaceconductive layer made of the second metal, e.g., the metal of theplatinum group except the iridium, is formed between the firstconductive layer and the second conductive layer. Therefore, the (111)intensities of the third conductive layer and the ferroelectric layercan be enhanced and thus the electric characteristics of theferroelectric capacitor can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a schematic sectional view showing a structure of acapacitor according to a first embodiment of the present invention;

[0027]FIG. 2 is a graph showing the diffusion of iridium in thecapacitor and the diffusion preventing effect;

[0028]FIGS. 3A to 3C are sectional views showing steps in a method ofmanufacturing the capacitor according to the first embodiment of thepresent invention;

[0029]FIG. 4 is a graph showing the dependency of the residual electriccharge amount on the substrate temperature in the capacitor according tothe first embodiment of the present invention;

[0030]FIG. 5 is a graph showing the dependency of the leakage current onthe substrate temperature in the capacitor according to the firstembodiment of the present invention;

[0031]FIG. 6 is a graph showing the dependency of the residual electriccharge amount on the gas flow rate ratio in the capacitor according tothe first embodiment of the present invention;

[0032]FIG. 7 is a schematic sectional view showing a structure of acapacitor according to a variation of the first embodiment of thepresent invention;

[0033]FIG. 8 is a schematic sectional view showing a structure of asemiconductor device according to a second embodiment of the presentinvention;

[0034]FIGS. 9A to 9J, and FIGS. 11A to 11C are sectional views showingsteps in a method of manufacturing the semiconductor device according tothe second embodiment of the present invention;

[0035]FIGS. 10A to 10E are sectional views showing steps in a method ofmanufacturing a capacitor according to a fourth embodiment of thepresent invention;

[0036]FIG. 11 is a view showing respective (111) integrated intensitiesof the lower electrode, that constitutes the capacitor according to thefourth embodiment of the present invention and the reference capacitorrespectively, and the PZT layer that is crystallized on the lowerelectrode;

[0037]FIG. 12 is a view showing the polarization saturation voltage ofthe ferroelectric capacitor due to the difference in respective lowerelectrode structures of the capacitor according to the fourth embodimentof the present invention and the reference capacitor;

[0038]FIG. 13 is a view showing the switching charge amount of theferroelectric capacitor at the applied voltage of 1.8 V due to thedifference in respective lower electrode structures of the capacitoraccording to the fourth embodiment of the present invention and thereference capacitor;

[0039]FIG. 14 is a view showing the switching charge amount of theferroelectric capacitor at the applied voltage of 3.0 V due to thedifference in respective lower electrode structures of the capacitoraccording to the fourth embodiment of the present invention and thereference capacitor;

[0040]FIG. 15 is a view showing the leakage current density of theferroelectric capacitor due to the difference in respective lowerelectrode structures of the capacitor according to the fourth embodimentof the present invention and the reference capacitor;

[0041]FIG. 16 is a view showing the fatigue loss characteristic of theferroelectric capacitor due to the difference in respective lowerelectrode structures of the capacitor according to the fourth embodimentof the present invention and the reference capacitor;

[0042]FIG. 17 is a view showing the retention characteristic of theferroelectric capacitor due to the difference in respective lowerelectrode structures of the capacitor according to the fourth embodimentof the present invention and the reference capacitor;

[0043]FIG. 18 is a sectional view showing another example of thecapacitor according to the fourth embodiment of the present invention;and

[0044]FIGS. 19A to 19K are sectional views showing steps ofmanufacturing a semiconductor device according to a fifth embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Embodiments of the present invention will be explained withreference to the accompanying drawings hereinafter.

[0046] (First Embodiment)

[0047] A semiconductor device having a capacitor according to a firstembodiment of the present invention and a method of manufacturing thesame will be explained with reference to FIG. 1 to FIG. 7 hereunder.

[0048]FIG. 1 is a schematic sectional view showing a structure of acapacitor according to a first embodiment. FIG. 2 is a graph showing thediffusion of iridium in the capacitor and the diffusion preventingeffect. FIGS. 3A to 3C are sectional views showing steps in a method ofmanufacturing the capacitor according to the first embodiment. FIG. 4 isa graph showing the dependency of the residual electric charge amount onthe substrate temperature in the capacitor according to the firstembodiment. FIG. 5 is a graph showing the dependency of the leakagecurrent on the substrate temperature in the capacitor according to thefirst embodiment. FIG. 6 is a graph showing the dependency of theresidual electric charge amount on the gas flow rate ratio in thecapacitor according to the first embodiment. FIG. 7 is a schematicsectional view showing a structure of a capacitor according to avariation of the first embodiment.

[0049] First, a structure of the capacitor according to the firstembodiment will be explained with reference to FIG. 1 hereunder.

[0050] An interlayer insulating layer 12 is formed on a siliconsubstrate 10. A contact hole 14 that reaches the silicon substrate 10 isformed in the interlayer insulating layer 12. A conductive plug 16 thatis connected electrically to the silicon substrate 10 is formed in thecontact hole 14. The capacitor having a lower electrode 30 that isformed by stacking an iridium layer 18, an iridium oxide layer 20, aplatinum oxide layer 22, and a platinum layer 24 sequentially, acapacitor dielectric layer 32 that is formed of the PZT layer formed onthe lower electrode 30, and an upper electrode 34 that is formed of theplatinum layer formed on the capacitor dielectric layer 32 is formed onthe interlayer insulating layer 12 in which the plug 16 is buried.

[0051] In this manner, the main feature of the capacitor according tothe first embodiment resides in that the lower electrode 30 is formed ofthe stacked layer consisting of the iridium layer 18, the iridium oxidelayer 20, the platinum oxide layer 22, and the platinum layer 24. Thereason for the structure that the lower electrode 30 is constructed bysuch stacked structure in the capacitor according to the firstembodiment will be explained hereunder.

[0052] The iridium layer 18 and the iridium oxide layer 20 are layersserving as the oxygen barrier. As described above, the platinum layer 24is the layer having the high oxygen permeability. Thus, unless theoxygen barrier layer is provided under the platinum layer 24, the oxygenis diffused toward the plug 16 in the course of the layer formation ofthe capacitor dielectric layer 32 or in the course of thecrystallization thereof and thus at least an upper surface of the plug16 is oxidized. If the iridium layer 18 and the iridium oxide layer 20,both having the low oxygen permeability, are provided between the plug16 and the platinum layer 24, the plug 16 is never oxidized in thecourse of the layer formation of the capacitor dielectric layer 32 or inthe course of the crystallization thereof. Thus, the contactcharacteristic between the plug 16 and the lower electrode 30 can beheld satisfactorily.

[0053] The reason for forming the iridium oxide layer 20 in addition tothe iridium layer 18 is to provide the sufficient orientation to theplatinum layer 24 formed thereon. The platinum layer 24 can be orientedonly by the iridium layer 18, but the orientation of the iridium layer18 is reflected on the platinum layer 24. In order to give thesufficient orientation to the platinum layer 24 much more, it is desiredthat the iridium oxide layer should be formed in addition to the iridiumlayer 18.

[0054] The platinum oxide layer 22 is the iridium diffusion preventinglayer that prevents the diffusion of the iridium from the oxygen barrierlayer (the iridium layer 18 and the iridium oxide layer 20) to thecapacitor dielectric layer 32. As described above, if the PZT layerdeposited by the sputter method is applied as the capacitor dielectriclayer 32, the iridium is diffused into the PZT layer from theiridium-based oxygen barrier layer via the Pt layer and thus the leakagecurrent of the capacitor is increased. Therefore, if the platinum oxidelayer 22 that has the high iridium diffusion preventing capability isformed on the oxygen barrier layer, the iridium can be prevented frombeing diffused into the PZT layer in the course of the annealing processas the post process. As a result, the crystallization of the capacitordielectric layer 32 can be achieved sufficiently and thus the capacitordielectric layer 32 having the desired dielectric constant can beformed.

[0055]FIG. 2 is a graph showing results of the iridium distribution inthe capacitor in the depth direction, which are measured by thesecondary ion mass spectrometry method. In FIG. 2, a dotted lineindicates the case where the electrode structure of the capacitoraccording to the first embodiment is employed, and a solid lineindicates the case where the Pt/IrO_(x)/Ir electrode structure in theprior art is employed. As shown in FIG. 2, the iridium is seldom watchedin the PZT layer in the capacitor according to the first embodimentindicated by the dotted line, but the iridium is watched at the highconcentration in the capacitor having the Pt/IrO_(x)/Ir electrodestructure indicated by the solid line. It can be understood from FIG. 2that the platinum oxide layer 22 that is provided between the platinumlayer 24 and the iridium oxide layer 20 of the lower electrode 30 hasthe iridium diffusion preventing action.

[0056] In this case, the mechanism for preventing the diffusion of theiridium by the platinum oxide layer 22 is not apparent. But it may beconsidered that the oxygen contained in the platinum oxide layer 22 hasthe important role to prevent the diffusion of the iridium.

[0057] The platinum layer 24 is the layer that is provided mainly tocontrol the orientation of the crystal of the capacitor dielectric layer32. The platinum layer 24 has the high conductivity and is effective forthe reduction in the resistance of the lower electrode 30. Also, thereis the merit such that the platinum layer 24 has the high melting pointand can withstand the high-temperature process in the course of theformation of the capacitor dielectric layer.

[0058] If the capacitor is constructed in this manner, the iridium layer18 functions as the oxygen barrier and the platinum oxide layer 22functions as the diffusion barrier of the iridium. For this reason, theentering of the oxygen in the course of the formation of the capacitordielectric layer 32 and the diffusion of the iridium into the capacitordielectric layer 32 can be prevented. Therefore, the capacitordielectric layer 32 having the desired dielectric constant can beformed, while maintaining the contact characteristic between the plug 16and the lower electrode 30.

[0059] The characteristics of the capacitor due to difference in thestructures in the first embodiment and the prior art are shown inTable 1. By way of comparison, the characteristic of the capacitorhaving the lower electrode that has the Pt/IrO_(x)/Ir structure, inwhich the iridium diffusion preventing layer is not provided, and thecharacteristic of the capacitor having the lower electrode that has thePt/Ti structure, which is widely employed in the planar-type capacitor,are also shown in Table 1. In this case, the residual electric chargeamount is measured at 3 V and the leakage current is measured at 6 V.TABLE 1 (A) (B) (C) (D) Pt/PtO_(x)/IrO_(x)/Ir 33.0 2.9 3.4 × 10⁻⁶Pt/IrO_(x)/Ir 35.0 4.5 4.0 × 10⁻² Pt/Ti 35.0 3.0 3.6 × 10⁻⁶

[0060] As shown in Table 1, the leakage current becomes in the order ofμA/cm² in the capacitor according to the first embodiment. In contrast,in the capacitor that has the lower electrode having the Pt/IrO_(x)/Irstructure in the prior art, it can be understood that the leakagecurrent is larger than the capacitor according to the first embodimentby about four figures and that the layer quality of the capacitordielectric layer is degraded by the diffusion of the iridium. Also,respective characteristics of the capacitor according to the firstembodiment are by no means inferior to the capacitor that has the lowerelectrode having the Pt/Ti structure and are satisfactory.

[0061] Next, a method of manufacturing the capacitor according to thefirst embodiment will be explained with reference to FIGS. 3A to 3Chereunder.

[0062] First, steps required until the structure shown in FIG. 3A isformed will be explained hereunder.

[0063] The interlayer insulating layer 12 made of the silicon oxidelayer is formed by depositing the silicon oxide layer of 700 nmthickness, for example, on the silicon substrate 10 by the CVD method,for example.

[0064] Then, the contact hole that reaches the silicon substrate 10 isformed in the interlayer insulating layer 12 by the lithography and thedry etching.

[0065] Then, a titanium (Ti) layer of 20 nm thickness, a titaniumnitride (TiN) layer of 10 nm thickness, and a tungsten (W) layer of 300nm thickness, for example, are deposited on the overall surface by theCVD method, for example.

[0066] Then, the plug 16 that consists of the stacked structure of theW/TiN/Ti structure and is buried in the contact hole 14 is formed bypolishing flat the tungsten layer, the titanium nitride layer, and thetitanium layer by virtue of the CMP (Chemical Mechanical Polishing)method, for example, until a surface of the interlayer insulating layer12 is exposed (FIG. 3A).

[0067] Next, steps required until the structure shown in FIG. 3B isformed will be explained.

[0068] The iridium layer 18 of 200 nm thickness, for example, is formedon the overall surface of the interlayer insulating layer 12 and theplug 16 by the sputter method, for example. For instance, the iridiumlayer 18 of 200 nm thickness is formed by growing the layer for 144seconds at the substrate temperature of 200° C., the power of 1 kW, andthe argon (Ar) gas flow rate of 100 sccm.

[0069] Then, the iridium oxide layer 20 of 30 nm thickness, for example,is formed on the iridium layer 18 by the sputter method, for example.For instance, the iridium oxide layer 20 of 30 nm thickness is formed bygrowing the layer for 11 seconds at the substrate temperature of 20° C.,the power of 1 kW, the argon gas flow rate of 25 sccm, and the oxygengas flow rate of 25 sccm.

[0070] Then, the platinum oxide layer 22 of 23 nm thickness, forexample, is formed on the iridium oxide layer 20 by the sputter method,for example. For instance, the platinum oxide layer 22 of 23 nmthickness is formed by growing the layer for 27 seconds at the substratetemperature of 350° C., the power of 1 kW, the argon gas flow rate of 36sccm, and the oxygen gas flow rate of 144 sccm.

[0071] As shown in FIG. 4, when the substrate temperature in forming theplatinum oxide layer 22 is lower than 200° C. or higher than 400° C.,the reduction in the residual electric charge amount appears. Also, asshown in FIG. 5, the substrate temperature in forming the platinum oxidelayer 22 is lower than 200° C. or higher than 400° C., the leakagecurrent is increased. Also, the oxygen is dissociated during the layerformation of the platinum oxide layer 22 at the substrate temperature ofmore than 400° C., so that the platinum layer is formed. Accordingly, itis desired that the substrate temperature in forming the platinum oxidelayer 22 should be set over 200° C. and below 400° C. Also, the residualelectric charge amount has the larger value if the layer formingtemperature becomes higher within the above temperature range.Therefore, it is desired that the substrate temperature in forming theplatinum oxide layer 22 should be set to the higher temperature withinthe above temperature range, e.g., the temperature of about 350° C.

[0072] In addition, the layer thickness of the platinum oxide layer 22is set to 23 nm in the above layer forming conditions, but the layerthickness of more than 15 nm may be appropriately selected. Theadhesiveness of the platinum oxide layer 22 is not sufficient if thelayer thickness is thinner than 15 nm, while the subsequent workabilityis degraded if the layer thickness is too thick. As a result, it isdesired that the layer thickness of the platinum oxide layer 22 shouldbe appropriately selected in response to the structure of the appliedsystem and process to exceed the layer thickness of 15 nm.

[0073] Also, in the above layer forming conditions, the gas flow rateratio in forming the platinum oxide layer 22 is set as Ar:O₂=1:4. Asshown in FIG. 6, if the gas flow rate ratio is changed in the range ofAr:O₂=7:2 to 1:9 (oxygen concentration 40 to 90%), the residual electriccharge amount in the formed capacitor is seldom changed. In other words,it may be considered that the gas flow rate ratio in forming theplatinum oxide layer 22 does not exert a bad influence upon the residualelectric charge amount. According to this, the gas flow rate ratio informing the platinum oxide layer 22 may be set to any value, andpreferably the oxygen concentration should be set to 40 to 80%.

[0074] Then, the platinum layer 24 of 100 nm thickness, for example, isformed on the platinum oxide layer 22 by the sputter method, forexample. For instance, the platinum layer 24 of 100 nm thickness isformed by growing the layer for 54 seconds at the substrate temperatureof 13° C., the power of 1 kW, and the argon gas flow rate of 100 sccm.

[0075] In this case, the substrate temperature in forming the platinumlayer 24 is set below 400° C. This is because the oxygen is dissociatedfrom the underlying platinum oxide layer 22 if the layer is formed atthe temperature of more than 400° C. and thus the iridium diffusionpreventing action is degraded.

[0076] Then, the rapid thermal annealing process is carried out at 600to 750° C. in the argon atmosphere to crystallize the platinum layer 24.Since the platinum layer 24 has the predetermined orientation by thisannealing process, it is possible to control the orientation of the PZTlayer to be formed later.

[0077] Then, a PZT layer 26 of 100 nm thickness, for example, is formedon the platinum layer 24 by the sputter method.

[0078] Then, the PZT layer 26 is crystallized by executing the rapidthermal annealing process at 750° C. in the oxygen atmosphere. At thistime, the PZT layer 26 is subjected to the orientation of the underlyingplatinum layer 24 and then oriented in (111). Also, since the platinumoxide layer 22 that functions as the iridium diffusion barrier layer isformed between the PZT layer 26 and the iridium oxide layer 20, theiridium is in no ways diffused into the PZT layer 26 even if suchhigh-temperature process is carried out.

[0079] Then, a platinum layer 28 of 100 nm thickness, for example, isformed on the PZT layer 26 by the sputter method, for example. Forinstance, the platinum layer 28 of 100 nm thickness is formed by growingthe layer for 54 seconds at the substrate temperature of 13° C., thepower of 1 kW, and the argon gas flow rate of 100 sccm (FIG. 3B).

[0080] Then, the lower electrode 30 consisting of the platinum layer24/the platinum oxide layer 22/the iridium oxide layer 20/the iridiumlayer 18, the capacitor dielectric layer 32 formed on the lowerelectrode 30 and consisting of the PZT layer, the upper electrode 34formed on the capacitor dielectric layer 32 and consisting of theplatinum layer are formed by patterning the platinum layer 28, the PZTlayer 26, the platinum layer 24, the platinum oxide layer 22, theiridium oxide layer 20, and the iridium layer 18 into the same shape byvirtue of the lithography and the dry etching (FIG. 3C).

[0081] In this fashion, the capacitor having the lower electrode 30consisting of the platinum layer 24/the platinum oxide layer 22/theiridium oxide layer 20/the iridium layer 18 can be formed.

[0082] As described above, according the first embodiment, the lowerelectrode 30 consisting of the platinum layer 24/the platinum oxidelayer 22/the iridium oxide layer 20/the iridium layer 18 is formed.Thus, the diffusion of the oxygen in the course of the layer formationof the capacitor dielectric layer 32 can be prevented by the iridiumoxide layer 20 and the iridium layer 18, and also the diffusion of theiridium from the oxygen diffusion barrier layer to the capacitordielectric layer 32 can be prevented by the platinum oxide layer 22.Therefore, even if the capacitor dielectric layer 32 is formed by thesputtering, the sufficient crystallization of the capacitor dielectriclayer can be achieved while preventing the diffusion of the iridium. Asa result, the high-performance ferroelectric capacitor having thedesired electric characteristics can be manufactured.

[0083] In the above first embodiment, the lower electrode 30 is formedof the stacked layer that consists of the iridium layer 18, the iridiumoxide layer 20, the platinum oxide layer 22, and the platinum layer 24.Either the iridium layer 18 or the iridium oxide layer 20 may beemployed as the layer that is used as the oxygen barrier. For example,as shown in FIG. 7, the lower electrode 30 may be formed of the stackedlayer that consists of the iridium layer 18, the platinum oxide layer22, and the platinum layer 24.

[0084] (Second Embodiment)

[0085] A semiconductor device and a method of manufacturing the sameaccording to a second embodiment of the present invention will beexplained with reference to FIG. 8 to FIGS. 11A to 11C hereunder.

[0086]FIG. 8 is a schematic sectional view showing a structure of asemiconductor device according to a second embodiment. FIGS. 9A to 9D,FIGS. 10A to 11C, and FIGS. 11A to 11C are sectional views showing stepsin a method of manufacturing the semiconductor device according to thesecond embodiment.

[0087] First of all, the structure of the semiconductor device accordingto the second embodiment will be explained with reference to FIG. 8hereunder.

[0088] An element isolation layer 42 is formed on a silicon substrate40. Memory cell transistors having gate electrodes 48 and source/draindiffusion layers 56 are formed in an element region that is defined bythe element isolation layer 42. An interlayer insulating layer 62 isformed on the silicon substrate 40 on which the memory cell transistorsare formed. Plugs 66 that are electrically connected to the source/draindiffusion layers 56 are buried in the interlayer insulating layer 62.

[0089] Lower electrodes 80 having the Pt/PtO_(x)/IrO_(x)/Ir structure isformed on the interlayer insulating layer 62 in which the plugs 66 areburied. Capacitor dielectric layers 82 made of PZT are formed on thelower electrodes 80 respectively. Upper electrodes 84 made of iridiumoxide are formed on the capacitor dielectric layers 82 respectively. Inthis manner, the ferroelectric capacitor is constructed by the lowerelectrode 80, the capacitor dielectric layer 82, and the upper electrode84.

[0090] A ferroelectric capacitor protection layer 86 and an interlayerinsulating layer 88 are formed on the interlayer insulating layer 62 onwhich the ferroelectric capacitors are formed. A plug 92 that isconnected electrically to the plugs 66 is buried in the interlayerinsulating layer 88 and the ferroelectric capacitor protection layer 86.A wiring layer 96 that is connected electrically to the source/draindiffusion layers 56 via the plugs 92, 66 and wiring layers 98 that areconnected electrically to the upper electrodes 84 are formed on theinterlayer insulating layer 88 in which the plug 92 is buried.

[0091] In this way, the feature of the semiconductor device according tothe second embodiment is that the capacitor lower electrode 80 of theferroelectric memory is constructed by the Pt/PtO_(x)/IrO_(x)/Irstructure like the lower electrode structure of the capacitor accordingto the first embodiment. If the ferroelectric memory is constructed inthis manner, the diffusion of the oxygen in the middle of the layerformation of the capacitor dielectric layer can be prevented by theiridium oxide layer and the iridium layer and also the diffusion of theiridium from the oxygen diffusion barrier layer to the capacitordielectric layer can be prevented by the platinum oxide layer.Accordingly, if the capacitor dielectric layer is formed by thesputtering, the sufficient crystallization of the capacitor dielectriclayer can be achieved with preventing the diffusion of the iridium. As aresult, the high performance ferroelectric memory having the desiredelectric characteristics can be manufactured.

[0092] Next, a method of manufacturing the semiconductor deviceaccording to the second embodiment will be explained with reference toFIGS. 9A to 9D to FIGS. 11A to 11C hereunder.

[0093] First, the element isolation layer 42 that is buried in thesilicon substrate 40 is formed on the silicon substrate 40 by theshallow trench method, for example.

[0094] Then, a P-well 44 is formed by ion-implanting the boron ion, forexample, into a memory cell forming region (FIG. 9A).

[0095] Then, a gate insulating layer 46 made of a silicon oxide layer isformed on an element region defined by the element isolation layer 42 byoxidizing a surface of the silicon substrate 40 by means of the thermaloxidation method, for example.

[0096] Then, a polysilicon layer and a silicon nitride layer aredeposited on the gate insulating layer 46 by the CVD method, forexample.

[0097] Then, the gate electrodes 48, upper surfaces of which are coveredwith a silicon nitride layer 50 and which are formed of the polysiliconlayer, are formed by patterning the silicon nitride layer and thepolysilicon layer into the same shape.

[0098] Then, impurity diffusion regions 52 are formed on the siliconsubstrate 40 on both sides of the gate electrodes 48 by implanting theion into the silicon substrate 40 while using the gate electrodes 48 asa mask (FIG. 9B).

[0099] Next, a silicon nitride layer is deposited on the overall surfaceby the CVD method, for example. Then, sidewall insulating layers 54 madeof the silicon nitride layer are formed on side walls of the gateelectrodes 48 and the silicon nitride layer 50 by etching back thesilicon nitride layer.

[0100] Then, impurity diffusion regions 52 b are formed on the siliconsubstrate 40 on both sides of the gate electrodes 48 by implanting theion into the silicon substrate 40 while using the gate electrodes 48 andthe sidewall insulating layers 54 as a mask. Accordingly, source/draindiffusion layers 56 consisting of the impurity diffusion regions 52 a,52 b are formed (FIG. 9C).

[0101] In this manner, memory cell transistors having the gateelectrodes 48 and the source/drain diffusion layers 56 are formed.

[0102] Then, a silicon nitride layer 58 of 20 nm thickness and a siliconoxide layer 60 of 700 nm thickness are deposited on the siliconsubstrate 40, on which the memory cell transistors are formed, by theCVD method, for example.

[0103] Then, the interlayer insulating layer 62, which are made of thesilicon nitride layer 58 and the silicon oxide layer 60 and a surface ofwhich is made flat, is formed by planarizing a surface of the siliconoxide layer 60 by virtue of the CMP method, for example.

[0104] Then, contact holes 64 reaching the silicon substrate 40 areformed in the interlayer insulating layer 62 by the lithography and thedry etching.

[0105] Then, the titanium layer of 20 nm thickness, the titanium nitridelayer of 10 nm thickness, and the tungsten layer of 300 nm thickness,for example, are deposited on the overall surface by the CVD method, forexample.

[0106] Then, the plugs 66 which have the stacked structure of theW/TiN/Ti structure and which are buried in the contact holes 64 areformed by polishing flat the tungsten layer, the titanium nitride layer,and the titanium layer until the surface of the interlayer insulatinglayer 62 is exposed by means of the CMP method, for example (FIG. 9D).

[0107] Next, like the lower electrode forming method in the capacitormanufacturing method according to the first embodiment, an iridium layer68 of 200 nm thickness, an iridium oxide layer 70 of 30 nm thickness, aplatinum oxide layer 72 of 23 nm thickness, and a platinum layer 74 of100 nm thickness, for example, are formed by the sputter method, forexample.

[0108] Then, the platinum layer 74 is crystallized by executing therapid thermal annealing process at 750° C. in the argon atmosphere.

[0109] Then, a PZT layer 76 of 200 nm thickness, for example, is formedon the platinum layer 74 by the sputter method. The PZT layer 76 of 200nm thickness is formed by growing the layer for 360 seconds at thesubstrate temperature of 13° C., the power of 1 kW, and the argon gasflow rate of 24 sccm, for example.

[0110] Then, the PZT layer 76 is crystallized by executing the rapidthermal annealing process at 750° C. in the oxygen atmosphere.

[0111] Then, an iridium oxide layer 78 of 200 nm thickness, for example,is formed on the PZT layer 76 by the sputter method, for example (FIG.9E). The iridium oxide layer 78 of 200 nm thickness is formed by growingthe layer for 81 seconds at the substrate temperature of 13° C., thepower of 1 kW, the argon gas flow rate of 100 sccm, and the oxygen gasflow rate of 100 sccm, for example.

[0112] Then, the lower electrodes 80 consisting of the platinum layer74/the platinum oxide layer 72/the iridium oxide layer 70/the iridiumlayer 68, the capacitor dielectric layers 82 formed on the lowerelectrodes 80 and consisting of the PZT layer, and the upper electrodes84 formed on the capacitor dielectric layers 82 and consisting of theiridium oxide layer are formed by patterning the iridium oxide layer 78,the PZT layer 76, the platinum layer 74, the platinum oxide layer 72,the iridium oxide layer 70, and the iridium layer 68 into the same shapeby virtue of the lithography and the dry etching (FIG. 9F).

[0113] In this fashion, the ferroelectric capacitors, which consist ofthe lower electrodes 80, the capacitor dielectric layers 82, and theupper electrodes 84 and in which the lower electrodes 80 areelectrically connected to the source/drain diffusion layers 56 via theplugs 66, are formed.

[0114] Then, the PZT layer of 40 nm thickness is formed on the entiresurface by the sputter method, for example. In this case, this PZT layerfunctions as the ferroelectric capacitor protection layer 86 (FIG. 9G).

[0115] Then, the silicon oxide layer of 1100 nm thickness is formed onthe ferroelectric capacitor protection layer 86 by the CVD method, forexample.

[0116] Then, an interlayer insulating layer 88 which is made of thesilicon oxide layer and whose surface is planarized is formed bypolishing a surface of the silicon oxide layer by means of the CMPmethod, for example (FIG. 9H). Then, contact holes 90 reaching the plugs66 are formed in the interlayer insulating layer 88 by the lithographyand the dry etching.

[0117] Then, the titanium layer of 20 nm thickness, the titanium nitridelayer of 10 nm thickness, and the tungsten layer of 300 nm thickness,for example, are deposited on the overall surface by the CVD method, forexample.

[0118] Then, the plug 92 that consists of the stacked structure of theW/TiN/Ti structure and is buried in the contact hole 90 is formed bypolishing flat the tungsten layer, the titanium nitride layer, and thetitanium layer by virtue of the CMP method, for example, until a surfaceof the interlayer insulating layer 88 is exposed (FIG. 11B).

[0119] Then, contact holes 94 reaching the upper electrodes 84 areformed in the interlayer insulating layer 88 by the lithography and thedry etching.

[0120] Then, the titanium layer of 60 nm thickness, the titanium oxidelayer of 30 nm thickness, the Au—Cu layer of 400 nm thickness, thetitanium layer of 5 nm thickness, and the titanium oxide layer of 70 nmthickness, for example, are deposited sequentially on the overallsurface by the sputter method, for example.

[0121] Then, a wiring layer 96 that is electrically connected to thesource/drain diffusion layer 56 via the plugs 66, 92 and wiring layers98 that are electrically connected to the upper electrodes 84 are formedby patterning the conductor having the TiN/Ti/Au—Cu/TiN/Ti structure, asshown FIG. 9J.

[0122] Like this, the ferroelectric memory having two transistors andtwo capacitors can be manufactured.

[0123] In this manner, according to the second embodiment, the capacitorlower electrode of the ferroelectric memory is constructed by thePt/PtO_(x)/IrO_(x)/Ir structure. Thus, the diffusion of the oxygen inthe course of the layer formation of the capacitor dielectric layer canbe prevented by the iridium oxide layer and the iridium layer, and alsothe diffusion of the iridium from the oxygen diffusion barrier layer tothe capacitor dielectric layer can be prevented by the platinum oxidelayer. Therefore, even if the capacitor dielectric layer is formed bythe sputtering, the sufficient crystallization of the capacitordielectric layer can be attained while preventing the diffusion of theiridium. As a result, the high performance ferroelectric memory havingthe desired electric characteristics can be fabricated.

[0124] In this case, in the above second embodiment, the capacitor shownin FIG. 1 according to the first embodiment is applied as the capacitorof the ferroelectric memory. But the ferroelectric memory may beconstructed by using the capacitor shown in FIG. 7 according to thevariation of the first embodiment.

[0125] (Third Embodiment)

[0126] The present invention is not limited to the above embodiments andvarious variations may be applied.

[0127] For example, in the above embodiments, the IrO_(x)/Ir structureand the Ir single-layer structure are shown as the oxygen diffusionbarrier layer. In order to prevent the diffusion of the oxygen, at leastthe IrO_(x) layer or the Ir layer may be formed between the plug and thecapacitor dielectric layer. Therefore, other conductive layer inaddition to the Ir/IrO_(x) structure, the IrO_(x) layer, the Ir layer,or the like may be formed. In this case, if the orientation control ofthe capacitor dielectric layer is taken into consideration, it isdesired that, as described above, the uppermost layer should be formedof IrO_(x).

[0128] Also, in the above embodiments, the platinum oxide layer isemployed as the iridium diffusion barrier layer, but such platinum oxidelayer may be employed by other conductive layer. There are the platinumgroup elements as the element having the property that is analogous tothe platinum. Ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os),iridium (Ir) belong to this group. It may be considered that theseelements other than the iridium can be applied as the iridium diffusionbarrier layer. Accordingly, it may be concluded that any one ofconductive oxides of these metal elements, i.e., RuO_(x), RhO_(x),PdO_(x), and OSO_(x) may be employed in place of the platinum oxidelayer.

[0129] Similarly, the ruthenium layer, the rhodium layer, the palladiumlayer, or the osmium layer may be employed in place of the platinumlayer that is formed on the iridium diffusion barrier layer.

[0130] Also, in the above embodiments, the case where the PZT layer isapplied as the capacitor dielectric layer is shown. The presentinvention can be similarly applied to the case where other capacitordielectric layer is employed. For example, the high-dielectric constantlayer such as the BST ((Ba, Sr)TiO₃) layer, the ST (SrTiO_(x)) layer,the Ta₂O₅ layer, etc. or the ferroelectric layer such as Y1, etc. can beapplied as the capacitor dielectric layer.

[0131] Also, in the above second embodiment, the case where thecapacitor according to the present invention is applied to theferroelectric memory is shown. But the capacitor according to thepresent invention can be applied to other semiconductor device. Forexample, DRAM may be constructed by using the capacitor according to thepresent invention, otherwise the capacitor according to the presentinvention may be employed as a single device.

[0132] Also, in the above embodiments, the platinum oxide layer isrepresented by PtO_(x) and also the iridium oxide layer is representedby IrO_(x). The composition ratio x of the oxygen in these metal oxidescan be appropriately selected. In the typical layer, the compositionratio x can be set in the range of 0<x≦2.

[0133] In this case, the iridium oxide may be formed instead of theplatinum as the upper electrode of the capacitor.

[0134] (Fourth Embodiment)

[0135] The lower electrodes of the capacitors shown in the first tothird embodiments have the structure in which the oxygen barrier layersuch as the Ir layer or the IrO_(x) layer, the iridium diffusionpreventing layer such as the PtO_(x) layer, and the underlyingdielectric layer such as the Pt layer are formed sequentially.

[0136] That is, the oxygen barrier layer has either the single layerstructure of the Ir layer or the double-layered structure consisting ofthe Ir layer and the IrO_(x) layer. Also, the iridium diffusionpreventing layer prevents the diffusion of Ir in the oxygen barrierlayer into the overlying PZT ferroelectric layer and is formed of themetal oxide that consists of the platinum group except Ir.

[0137] However, there is such a tendency that the (111) orientation ofthe uppermost Pt layer becomes weak in the lower electrode having suchlayer structure.

[0138] For example, like the first embodiment, the ferroelectriccharacteristic obtained when the PZT layer formed on the lower electrodehaving the structure, in which the Ir layer, the IrO_(x) layer, thePtO_(x) layer, and the Pt layer are formed sequentially, is annealed tocrystallize is not good rather than the ferroelectric characteristicobtained when the PZT layer formed on the lower electrode having thestructure, in which the Ti layer and the Pt layer are formedsequentially, is annealed to crystallize.

[0139] Therefore, in the fourth embodiment and embodiments describedlater, the capacitor that has the oxygen barrier layer and the iridiumdiffusion preventing layer and also the orientation improving interfacelayer for enhancing the (111) plane orientation of the Pt layer servingas the underlying layer of the ferroelectric layer as the structure ofthe lower electrode will be explained hereunder.

[0140]FIGS. 10A to 10E are sectional views showing steps of forming acapacitor according to a fourth embodiment of the present invention. Thesame references as those in FIG. 1 denote the same elements.

[0141] First, steps required until the structure shown in FIG. 10A isformed will be explained hereunder.

[0142] The interlayer insulating layer 12 made of SiO₂ is formed on thesilicon substrate 10 on which the impurity diffusion region 10 a isformed. Then, the contact hole 14 is formed o the impurity diffusionregion 10 a by etching the interlayer insulating layer 12 while usingthe resist pattern (not shown). Then, the titanium nitride (TiN) layerand the tungsten (W) layer are formed sequentially in the contact hole14, and then the TiN layer and the W layer formed on the upper surfaceof the interlayer insulating layer 12 are removed by the CMP method.Accordingly, the W layer and the TiN layer left in the contact hole 14are employed as the conductive plug 16.

[0143] Then, as shown in FIG. 10B, the iridium (Ir) layer 18, theiridium oxide (IrO_(x)) layer 20, the first platinum (Pt) layer 21, theplatinum oxide (PtO_(x)) layer 22, and the second platinum (Pt) layer 24are formed sequentially on the plug 16 and the interlayer insulatinglayer 12 as the lower electrode conductive layer 17.

[0144] The Ir layer 18 of 200 nm thickness is formed by virtue of thesputter method by growing the layer for the growing time of 144 secondsat the substrate temperature of 400° C. and the power of 1 kW whileintroducing the argon (Ar) gas into the growth atmosphere at the flowrate of 100 sccm, for example.

[0145] The IrO_(x) layer 20 of 28 nm thickness is formed by virtue ofthe sputter method by growing the layer for the growing time of 10seconds at the substrate temperature of 400° C. and the power of 1 kWwhile introducing the argon (Ar) gas and the oxygen (O₂) gas into thegrowth atmosphere at the flow rates of 60 sccm and 20 sccm respectively,for example. According to such conditions, the composition ratio x ofthe oxygen (O) in the IrO_(x) layer is x=1 to 1.2 to give the metallicstructure. In this case, if the flow rates of both the Ar gas and theoxygen gas are set to 40 sccm in the forming conditions of the IrO_(x)layer 20, the composition ratio x becomes larger than 1.2. In this case,the composition ratio x of the IrO_(x) layer 20 is 0<x<2, for example.

[0146] The first Pt layer 21 is the Pt-interface layer to control thecrystal orientation of the platinum oxide (PtO_(x)) layer 22 and thesecond platinum (Pt) layer 24. For example, the first Pt layer 21 of 5nm thickness is formed by virtue of the sputter method by growing thelayer for the growing time of 4 seconds at the substrate temperature of350° C. and the power of 1 kW while introducing the Ar gas into thegrowth atmosphere at the flow rate of 100 sccm.

[0147] The PtO_(x) layer 22 of 30 nm thickness is formed by virtue ofthe sputter method by growing the layer for the growing time of 27seconds at the substrate temperature of 350° C. and the power of 1 kWwhile introducing the Ar gas and the oxygen (O₂) gas into the growthatmosphere at the flow rates of 36 sccm and 144 sccm respectively. Thecomposition ratio x of the PtO_(x) layer 22 is 0<x<2, for example.

[0148] The second Pt layer 24 of 50 nm thickness is formed by virtue ofthe sputter method by growing the layer for the growing time of 34seconds at the substrate temperature of 100° C. and the power of 1 kWwhile introducing the Ar gas into the growth atmosphere at the flow rateof 100 sccm.

[0149] After this, the second Pt layer 24 is crystallized by executingthe rapid thermal annealing process for 60 seconds at 750° C. in theargon introduced atmosphere.

[0150] Next, as shown in FIG. 10C, the PZT (Pb(Zr_(x), Ti_(1-x))O₃)layer 26 is formed on the second Pt layer 24 as the ferroelectric layerby the sputter method to have a thickness of 100 nm. In addition, themethod of forming the ferroelectric layer 26 are the MOD (Metal OrganicDeposition) method, the MOCVD (Metal Organic CVD) method, the sol-gelmethod, and others. Also, as the material of the ferroelectric layer 26,in addition to PZT, other PZT-based material such as PLCSZT, PLZT, etc.,the Bi layer structure compound material such as SBT (SrBi₂Ta₂O₉),SrBi₂(Ta, Nb)₂O₉, etc., and other metal oxide ferroelectric substancemay be employed. Also, if the high-dielectric capacitor is to be formed,the high-dielectric layer such as Ba_(x)Sr_(1-x)TiO₃, SrTiO₃, PLZT, etc.is formed in place of the ferroelectric layer.

[0151] Then, the PZT layer 26 is crystallized by executing the rapidthermal annealing process at 750° C.

[0152] Then, as shown in FIG. 10D, the IrO_(x) layer is formed on thePZT layer 26 as an upper electrode conductive layer 27. In this case,the Pt layer may be formed instead of the IrO_(x) layer as the upperelectrode conductive layer 27.

[0153] After this, as shown in FIG. 10E, the capacitor Q is formed bypatterning the upper electrode conductive layer 27, the PZT layer 26,and the lower electrode conductive layer 17 by means of thephotolithography method. According to this patterning, the upperelectrode conductive layer 27 is formed into the upper electrode 34 a ofthe capacitor Q, the PZT layer 26 is formed into the dielectric layer 32a of the capacitor Q, and the lower electrode conductive layer 17 isformed into the lower electrode 30 a of the capacitor Q.

[0154] By the way, the polarization direction of the PZT layer 26 is(001), but it is very difficult to orient the polarization direction to(001). Therefore, it is normal that the crystal of the PZT layer 26 isoriented in the (111) direction to increase the residual polarization(switching) of the PZT layer 26.

[0155] For this reason, it is preferable that the PZT layer 26 that isformed on the lower electrode conductive layer 17 in the capacitor Qforming steps should be oriented in the (111) plane direction to reflectthe orientation of the second Pt layer 24 as the underlying layer.

[0156] Thus, it is checked experimentally to what extent the differencein the (111) integrated intensity of the second Pt layer 24 and the(111) integrated intensity of the PZT layer is caused depending onwhether or not the Pt-interface layer 21 out of plural layersconstituting the above lower electrode 30 a is provided.

[0157] As the reference, the capacitor having the lower electrode inwhich the Ir layer, the IrO_(x) layer, the PtO_(x) layer, and the Ptlayer are formed sequentially, the PZT dielectric layer that iscrystallized on the lower electrode, and the IrO_(x) upper electrode isemployed. In the reference capacitor, when the (111) integratedintensity of the Pt layer constituting the lower electrode is measuredby the X-ray diffraction method and also the (111) integrated intensityof the PZT dielectric layer is measured by the X-ray diffraction method,the result shown by “REF” in FIG. 11 is derived.

[0158] In addition, in the capacitor Q shown in FIG. 10E according tothe fourth embodiment, when the (111) integrated intensity of the secondPt layer 24 constituting the lower electrode 30 a having thePt-interface layer 21 is measured by the X-ray diffraction method andalso the (111) integrated intensity of the overlying PZT layer 26 ismeasured by the X-ray diffraction method, the result shown by“Pt-Interface” in FIG. 11 is derived.

[0159] According to FIG. 11, the (111) integrated intensity of the Ptlayer 24 in the lower electrode 30 a having the Pt/PtO_(x)/Pt/IrO_(x)/Irstructure in the capacitor Q of the fourth embodiment becomes higherthan the (111) integrated intensity of the Pt layer as the uppermostlayer in the lower electrode having the Pt/PtO_(x)/IrO_(x)/Ir structurein the reference capacitor by 15%. Also, the (111) integrated intensityof the PZT layer 26 in the capacitor Q of the fourth embodiment becomeshigher than the (111) integrated intensity of the PZT layer in thereference capacitor by 18%.

[0160] Next, the difference in the polarization saturation voltage ofthe ferroelectric capacitor due to whether or not the Pt-interface layeris provided in the lower electrode structure will be explainedhereunder.

[0161] As the reference, the capacitor Q₀ having the lower electrode inwhich the Ir layer, the IrO_(x) layer, the PtO_(x) layer, and the Ptlayer are formed sequentially, the PZT dielectric layer that iscrystallized on the lower electrode, and the IrO_(x) upper electrode isprepared.

[0162] Also, as the capacitor according to the fourth embodiment, thecapacitor having the structure shown in FIG. 10E is employed. Thedifference in the polarization saturation voltage of the capacitoraccording to the fourth embodiment caused when the forming conditions ofthe IrO_(x) layer 20 in the Pt/PtO_(x)/Pt/IrO_(x)/Ir structureconstituting the lower electrode 30 a of the capacitor according to thefourth embodiment are changed is also examined. In the formingconditions of the IrO_(x) layer 20, only flow rates of the argon and theoxygen supplied to the sputter atmosphere are changed but otherconditions are not changed. In order to form the IrO_(x) layer 20, theflow rate of argon is set to 40 sccm and the flow rate of oxygen is setto 40 sccm in the first condition, while the flow rate of argon is setto 60 sccm and the flow rate of oxygen is set to 20 sccm in the secondcondition. The IrO_(x) layer formed in the second condition is moremetallic than the IrO_(x) layer formed in the first condition.

[0163] When the polarization saturation voltages of the capacitor Q₁₁according to the fourth embodiment that has the IrO_(x) layer 20 formedin the first condition in the lower electrode 30 a, the capacitor Q₁₂according to the fourth embodiment that has the IrO_(x) layer 20 formedin the second condition in the lower electrode 30 a, and the referencecapacitor Q₀ are measured respectively, results shown in FIG. 12 arederived. In this case, the planar shape of respective capacitors Q₀,Q₁₁, Q₁₂ used in measurement has a size of 50 μm×50 μm.

[0164] In order to examine the polarization saturation voltage, thehysteresis characteristics of the capacitors Q₀, Q₁₁, Q₁₂ are measuredby using the Sawyer-Tower Circuit. Then, the voltage change in the loadcapacitor is measured as the polarization change of the capacitor inresponse to the change in the applied voltage. In this case, thepolarization inversion charge amount (switching charge amount) isexamined by using the triangular wave of 1.2 V to 3.0 V as the appliedvoltage. The polarization saturation voltage is defined as the voltagethat causes the switching charge amount to reach 90% of the saturationvalue.

[0165] According to FIG. 12, the polarization saturation voltage of thecapacitor Q₁₁ according to the fourth embodiment that has the IrO_(x)layer 20 formed in the first condition in the lower electrode 30 abecomes lower than the polarization saturation voltage of the referencecapacitor Q₀ by 0.1 V. Also, the polarization saturation voltage of thecapacitor Q₁₂ according to the fourth embodiment that has the IrO_(x)layer 20 metallized by the second condition in the lower electrode 30 abecomes lower than the polarization saturation voltage of the referencecapacitor Q₀ by 0.2 V.

[0166] As a result, it is found that, if the Pt-interface layer 21 isformed between the PtO_(x) layer 22 and the IrO_(x) layer 20 like thecapacitors Q₁₁, Q₁₂ according to the fourth embodiment, the (111)orientation of the second Pt layer 24 and the PZT layer 26 is enhancedand also the polarization saturation voltage of them is lowered than thereference capacitor Q₀.

[0167] Also, it is found that, even in the capacitor according to thefourth embodiment, the smaller oxygen amount contained in the IrO_(x)layer 20 constituting the lower electrode 30 a contributes the reductionin the polarization saturation voltage of the capacitor.

[0168] In FIG. 12, the measurement of the polarization saturationvoltage of respective capacitors Q₀, Q₁₁, Q₁₂ is carried out pluraltimes respectively. The vertical line indicates the range in which ameasured value appears in the measurement, and the portion shown by atetragon indicates the range in which the measured values are convergedin the vertical line.

[0169] Next, the difference in the switching charge amount of theferroelectric capacitor due to whether or not the Pt-interface layer isprovided in the lower electrode structure will be explained hereunder.

[0170] As the reference, the reference capacitor Q₀ having the samestructure as that used in the test in FIG. 12 is employed. Also, as thecapacitor according to the fourth embodiment, like the capacitor used inthe test in FIG. 12, the capacitor Q₁₁ that has the IrO_(x) layer 20formed in the first condition in the lower electrode 30 a and thecapacitor Q₁₂ that has the metallic IrO_(x) layer 20 formed in thesecond condition in the lower electrode 30 a are employed. Thecapacitors Q₁₁, Q₁₂ according to the fourth embodiment have thePt-interface layer 21, unlike the reference capacitor Q₀. In this case,the planar shape of respective capacitors Q₀, Q₁₁, Q₁₂ used inmeasurement has a size of 50 μm×50 μm.

[0171] When the switching charge amount is examined if the appliedvoltage to the capacitors Q₀, Q₁₁, Q₁₂ is set to 1.8 V, results shown inFIG. 13 are derived. Also, when the switching charge amount is examinedif the applied voltage is set to 3.0 V, results shown in FIG. 14 arederived.

[0172] In FIG. 13, the switching charge amount of the capacitor Q₁₁according to the fourth embodiment that has the IrO_(x) layer 20 formedin the first condition in the lower electrode 30 a becomes higher thanthe switching charge amount of the reference capacitor Q₀ by about 4μC/cm². Also, the switching charge amount of the capacitor Q₁₂ accordingto the fourth embodiment that has the IrO_(x) layer 20 metallized by thesecond condition in the lower electrode 30 a becomes higher than theswitching charge amount of the reference capacitor Q₀ by about 2 μC/cm².

[0173] Also, according to FIG. 14, the switching charge amount of thecapacitor Q₁₁ according to the fourth embodiment that has the IrO_(x)layer 20 formed in the first condition in the lower electrode 30 abecomes higher than the switching charge amount of the referencecapacitor Q₀ by about 2 μC/cm². Also, the switching charge amount of thecapacitor Q₁₂ according to the fourth embodiment that has the IrO_(x)layer 20 metallized by the second condition in the lower electrode 30 abecomes higher than the switching charge amount of the referencecapacitor Q₀ by about 2 μC/cm².

[0174] As a result, it is found that, if the Pt-interface layer 21 isformed between the PtO_(x) layer 22 and the IrO_(x) layer 20 in thelower electrode 30 a like the capacitors Q₁₁, Q₁₂ according to thefourth embodiment, the (111) orientation of the second Pt layer 24 andthe PZT layer 26 is enhanced rather than the reference capacitor Q₀ andalso the switching charge amount of them is increased rather than thereference capacitor Q₀.

[0175] In FIG. 12 and FIG. 14, the measurement of the polarizationsaturation voltage of respective capacitors Q₀, Q₁₁, Q₁₂ is carried outplural times respectively. The vertical line indicates the range inwhich a measured value appears in the measurement, and the portion shownby a tetragon indicates the range in which the measured values areconverged in the vertical line.

[0176] Next, respective examined results of the leakage current density,the fatigue loss, and the retention characteristic of the ferroelectriccapacitor due to the difference in respective lower electrode structureswill be explained hereunder.

[0177] As the reference used in these examinations, the capacitor Q₀having the same structure as that employed in the test in FIG. 11 isemployed. Also, as the capacitor used in these examinations according tothe fourth embodiment, like the capacitor used in FIG. 11, the capacitorQ₁₁ that has the IrO_(x) layer 20 formed in the first condition in thelower electrode 30 a and the capacitor Q₁₂ that has the metallic IrO_(x)layer 20 formed in the second condition in the lower electrode 30 a areemployed. Both the capacitors Q₁₁, Q₁₂ according to the fourthembodiment have the Pt-interface layer 21. In this case, the planarshape of respective capacitors Q₀, Q₁₁, Q₁₂ used in measurement is setto the size of 50 μm×50 μm.

[0178] First, examined results of the leakage current density of threetypes of the capacitors Q₀, Q₁₁, Q₁₂ that have the lower electrodeshaving different structures are shown in FIG. 15. The measurement of theleakage current density of respective capacitors Q₀, Q₁₁, Q₁₂ is carriedout plural times respectively. The vertical line indicates the range inwhich a measured value appears in the measurement, and the portion shownby the tetragon indicates the range in which the measured values areconverged in the vertical line.

[0179] In FIG. 15, the leakage current of the reference capacitor Q₀that does not have the Pt-interface layer in the lower electrode isabout 1×10^(−3.75) A/cm² to 1×10^(−2.90) A/cm². Also, the leakagecurrent of the capacitor Q₁₁ according to the fourth embodiment that hasthe IrO_(x) layer 20 formed in the first condition in the lowerelectrode 30 a is about 1×10^(−3.45) A/cm² to 1×10^(−3.98) A/cm². Also,the leakage current of the capacitor Q₁₂ according to the fourthembodiment that has the metallic IrO_(x) layer 20 formed in the secondcondition in the lower electrode 30 a is about 1×10^(−3.0) A/cm² to1×10^(−2.90) A/cm². In this case, the measurement of the leakage currentis carried out by applying the voltage of 6V between the upper electrodeand the lower electrode of respective capacitors Q₀, Q₁₁, Q₁₂.

[0180] According to FIG. 15, it is found that the leakage current is notso different between the reference capacitor Q₀ and the capacitors Q₁₁,Q₁₂ according to the fourth embodiment. This is because the diffusion ofIr into the PZT layer 26 can be prevented by the PtO_(x) layer 22. As aresult, it is found that the lower electrode 30 a of the capacitors Q₁₁,Q₁₂ according to the fourth embodiment has the leakage currentpreventing effect.

[0181] Next, examined results of the fatigue loss of the PZT layer ofthree types of the capacitors Q₀, Q₁₁, Q₁₂ that have the lowerelectrodes having different structures are shown in FIG. 16. Themeasurement of the fatigue loss of respective capacitors Q₀, Q₁₁, Q₁₂ iscarried out plural times respectively. The vertical line indicates therange in which a measured value appears in the measurement, and theportion shown by a tetragon indicates the range in which the measuredvalues are converged in the vertical line.

[0182] The fatigue loss is measured by applying the voltage of ±7.0 V torespective capacitors Q₀, Q₁₁, Q₁₂ as the examined object to cause thepolarization, setting the operation cycle of the polarization inversionto 250 ns, and comparing the polarization charge amount obtained after2.880×10⁷ cycles with the initial polarization charge amount.

[0183] In FIG. 16, the fatigue loss of the capacitor Q₁₁ according tothe fourth embodiment that has the IrO_(x) layer 20 formed in the firstcondition in the lower electrode 30 a becomes lower than the fatigueloss of the reference capacitor Q₀ by about 10%. Also, the fatigue lossof the capacitor Q₁₂ according to the fourth embodiment that has themetallic IrO_(x) layer 20 formed in the second condition in the lowerelectrode 30 a becomes lower than the fatigue loss of the referencecapacitor Q₀ by about 15%.

[0184] In other words, according to the capacitors Q₁₁, Q₁₂ of thefourth embodiment, it is found that, because the Pt-interface layer isinserted between the PtO_(x) layer 22 and the IrO_(x) layer 20 in thelower electrode 30 a, the (111) orientation of the second Pt layer 24and the PZT layer 26 can be enhanced to improve the layer quality andthus the fatigue loss can be reduced. In addition, it is found that, ifthe IrO_(x) layer 20 constituting the lower electrode 30 a is metallizedby reducing the oxygen concentration, the layer quality of the PZT layercan be further improved and the fatigue loss can be reduced much more.

[0185] Next, respective examined results of the retention characteristicof the PZT layer of three types of the capacitors Q₀, Q₁₁, Q₁₂ that havethe lower electrodes having different structures are shown in FIG. 17.The measurement of the retention characteristic of respective capacitorsQ₀, Q₁₁, Q₁₂ is carried out plural times respectively. The vertical lineindicates the range in which a measured value appears in themeasurement, and the portion shown by the tetragon indicates the rangein which the measured values are converged in the vertical line.

[0186] The retention characteristic is the polarization holdingcharacteristic such that the polarization electric charge value isreduced with the lapse of time after the capacitor is polarized in onedirection by the applied voltage.

[0187] In the measurement of the retention characteristic, in case thecapacitor is polarized into the (+) direction by applying 3 V, forexample, to the upper electrode and then such capacitor is left as it isfor a predetermined time at the temperature of 150° C., and in case thecapacitor is polarized into the (−) direction by applying −3 V, forexample, to the upper electrode and then such capacitor is left as it isfor a predetermined time at the temperature of 150° C., the held amounts(reduced amount) of the polarization value are measured respectively.

[0188]FIG. 17 shows the polarization holding amount Q₂ (88) ofrespective capacitors after such polarized capacitors Q₀, Q₁₁, Q₁₂ areleft as they are for 88 hours at the temperature of 150° C. According toFIG. 17, if the capacitors Q₁₁, Q₁₂ according to the fourth embodimentin which the Pt-interface layer 21 is inserted between the PtO_(x) layer22 and the IrO_(x) layer 20 in the lower electrode 30 a are comparedwith the reference capacitor Q₀ that does not have the Pt-interfacelayer in the lower electrode, the layer quality of the PZT layer 26 canbe improved and thus the retention characteristic can be increased byabout 2 μC/cm².

[0189] As descried above, numerical values of the electriccharacteristics of the capacitors Q₁₁, Q₁₂ according to the fourthembodiment are equal satisfactorily to the planar-type capacitor thatemploys the lower titanium layer/upper platinum (Pt/Ti) structure as thelower electrode. In particular, the capacitors Q₁₁, Q₁₂ according to thefourth embodiment can overcome the important subjects that areindispensable to the development of the next-generation FeRAM, e.g., theswitching electric charge amount at the low voltage is enhanced, etc.

[0190] When the adhesiveness test of the lower electrode 30 a of thecapacitors Q₁₁, Q₁₂ according to the fourth embodiment is executed, thepeeling is difficult to occur at the interface between the PtO_(x) layer22 and the IrO_(x) layer 20 rather than the lower electrode in which thePt-interface layer 21 is not provided between the PtO_(x) layer 22 andthe IrO_(x) layer 20. Also, it is found that, if the oxygen compositionratio x in the IrO_(x) layer 20 as the underlying layer of thePt-interface layer 21 is reduced into 1 to 1.2, for example, even in thelower electrode 30 a that has the Pt-interface layer 21, the defectoccurring ratio in the adhesiveness between the PtO_(x) layer 22 and theIrO_(x) layer 20 can be reduced into about {fraction (1/7)} and thus theeffect of improving the adhesiveness of the multi-layered layerconstituting the lower electrode 30 a becomes remarkable.

[0191] In this case, the adhesiveness test is executed by the tensiontest by which the epoxy resin is pulled after such epoxy resin is pastedon the upper electrode of the capacitor and then dried for one hour at150° C.

[0192] Meanwhile, as described above, the IrO_(x) layer may be removedfrom the lower electrode 30 a having the Pt/PtO_(x)/IrO_(x)/Irstructure, or the lower electrode 30 b having the Pt/PtO_(x)/Pt/Irstructure (30 b) shown in FIG. 18 may be employed. In this case, thelayer quality of the PZT layer 26 formed on the lower electrode 30 b canbe improved by the presence of the Pt-interface layer 21. Also, in thelower electrode 30 b having the Pt/PtO_(x)/Pt/Ir structure, thelowermost Ir layer 18 is the oxygen barrier layer, the first Pt layer(Pt-interface layer) 21 is the orientation enhancing and densityimproving layer, the PtO_(x) layer 22 is the iridium diffusionpreventing layer, and the uppermost second Pt layer 23 is theorientation control layer of the PZT layer 26.

[0193] In the lower electrode 30 a, the rhodium layer or the palladiumlayer may be formed in place of the second Pt layer 24, the rutheniumlayer may be formed in place of the Ir layer 18, and the ruthenium oxidelayer may be formed in place of the IrO_(x) layer 20. Also, respectivemetal layers or metal oxide layers constituting the lower electrode 30 aare not limited to above layer thicknesses. It is preferable that thelayer thickness of the Pt-interface layer 21 should be within the rangeof 3 to 50 nm.

[0194] (Fifth Embodiment)

[0195]FIGS. 19A to 19K are sectional views showing steps ofmanufacturing an FeRAM memory cell according to a fifth embodiment ofthe present invention.

[0196] First, steps required until the sectional structure shown in FIG.19A is obtained will be explained hereunder.

[0197] As shown in FIG. 19A, an element isolation trench is formedaround a transistor forming region of an n-type or p-type silicon(semiconductor) substrate 40 by the photolithography method. Then, anelement isolation layer 42 is formed by filling silicon oxide (SiO₂) inthe element isolation trench. The element isolation layer 42 having suchstructure is called STI (Shallow Trench Isolation). In this case, aninsulating layer formed by the LOCOS (Local Oxidation of Silicon) methodmay be employed as the element isolation layer.

[0198] Then, a P-well 44 is formed by introducing a p-type impurity intothe transistor forming region of the silicon substrate 40. Then, asilicon oxide layer serving as the gate insulating layer 46 is formed bythermally oxidizing a surface of the transistor forming region of thesilicon substrate 40.

[0199] Then, an amorphous silicon layer or polysilicon layer and asilicon nitride layer are formed sequentially on the overall uppersurface of the silicon substrate 40. Then, the gate electrodes 48 a, 48b on which the silicon nitride layer 50 is stacked are formed bypatterning the silicon layer and the silicon nitride layer by virtue ofthe photolithography method.

[0200] In this case, two gate electrodes 48 a, 48 b are formed inparallel on one p-well 44. These gate electrodes 48 a, 48 b constitute apart of the word line.

[0201] Then, first to third n-type impurity diffusion regions 56 a to 56c serving as the source/drain are formed by ion-implanting the n-typeimpurity into the p-well 44 both sides of the gate electrodes 48 a, 48b.

[0202] Then, the insulating layer, e.g., the silicon oxide (SiO₂) layer,is formed on the overall surface of the silicon substrate 40 by the CVDmethod. Then, the insulating layer is etched back and is left asinsulating sidewall spacers 54 on both sides of the gate electrodes 48a, 48 b.

[0203] Then, the high-concentration impurity regions 52 a to 52 c areformed by ion-implanting the n-type impurity into the first to thirdn-type impurity diffusion regions 56 a to 56 c while using the gateelectrodes 48 a, 48 b and the sidewall spacers 54 as a mask. Thus, thefirst to third n-type impurity diffusion regions 56 a to 56 c are formedas the LDD structure.

[0204] The first n-type impurity diffusion region 56 a formed betweentwo gate electrodes 48 a, 48 b in one transistor forming region isconnected electrically to the bit line, while the second and thirdn-type impurity diffusion regions 56 b, 56 c formed on both sides of thetransistor forming region are connected electrically to the lowerelectrode of the capacitor described later.

[0205] According to the above steps, two MOS transistors T₁, T₂ havingthe gate electrodes 48 a, 48 b and the n-type impurity diffusion regions56 a to 56 c are formed in the p-well 44.

[0206] Then, a silicon oxide nitride (SiON) layer of about 200 nmthickness, which serves as the cover insulating layer 58 for coveringthe MOS transistors T₁, T₂, is formed on the overall surface of thesilicon substrate 40 by the plasma CVD method. Then, the silicon oxidelayer 60 of about 1.0 μm thickness is formed on the cover insulatinglayer 58 by the plasma CVD method using the TEOS gas.

[0207] Then, the silicon oxide layer 60 is thermally treated for 30minutes at the temperature of 700° C. in the nitrogen atmosphere at thenormal pressure, for example, as the densifying process of the siliconoxide layer 60. After this, the upper surface of the silicon oxide layer60 is planarized by the chemical mechanical polishing (CMP) method.

[0208] In this case, the silicon oxide layer 60 and the cover insulatinglayer 58 constitute the first interlayer insulating layer 62.

[0209] Next, steps required until the state shown in FIG. 19B isobtained will be explained hereunder.

[0210] First, a first contact hole 64 a having a depth that reaches thefirst impurity diffusion region 56 a is formed by patterning the firstinterlayer insulating layer 62 by means of the photolithography method.Then, the titanium nitride (TiN) layer of 50 nm thickness is formed as aglue layer on the first interlayer insulating layer 62 and in the firstcontact hole 64 a by the sputter method. In addition, the first contacthole 64 a is perfectly buried by growing the tungsten (W) layer on theTiN layer by virtue of the CVD method using WF₆.

[0211] Then, the W layer and the TiN layer are removed from the uppersurface of the first interlayer insulating layer 62 by polishing them bymeans of the CMP method. The tungsten layer and the TiN layer left inthe first contact hole 64 a are used as a first conductive plug 66 a.

[0212] Then, an oxidation preventing insulating layer 63 a made ofsilicon nitride (Si₃N₄) having a 100 nm thickness and an underlyinginsulating layer 63 b made of SiO₂ having a 100 nm thickness are formedsequentially on the first interlayer insulating layer 62 and the firstconductive plug 66 a by the plasma CVD method. The SiO₂ layer is grownby the plasma CVD method using TEOS. The oxidation preventing insulatinglayer 63 a is formed to prevent the event that the first conductive plug66 a is excessively oxidized by the heating process such as the laterannealing, etc. to occur the contact failure. It is desired that thethickness of the oxidation preventing insulating layer 63 a should beset to 70 nm or more, for example.

[0213] Next, steps required until the state shown in FIG. 19C isobtained will be explained hereunder.

[0214] First, second and third contact holes 64 b, 64 c are formed onthe second and third impurity diffusion regions 56 b, 56 c by etchingthe oxidation preventing insulating layer 63 a, the underlyinginsulating layer 63 b, and the first interlayer insulating layer 62while using the resist pattern (not shown).

[0215] Then, the Ti layer of 20 nm thickness and the TiN layer of 50 nmthickness are formed as the glue layer on the underlying insulatinglayer 63 b and in the second and third contact holes 64 b, 64 c by thesputter method. Then, the second and third contact holes 64 b, 64 c areburied perfectly by growing the W layer on the TiN layer by means of theCVD method.

[0216] In turn, the W layer and the TiN layer and the Ti layer areremoved from the upper surface of the underlying insulating layer 63 bby polishing them by virtue of the CMP method. Accordingly, the W layerand the TiN layer and the Ti layer left in the second and third contactholes 64 b, 64 c are used as second and third conductive plugs 66 b, 66c respectively.

[0217] Next, steps required until the structure shown in FIG. 19D isformed will be explained hereunder.

[0218] First, as shown in FIG. 19D, the iridium (Ir) layer 18 and theiridium oxide (IrO_(x)) layer 20 are formed on the second and thirdconductive plugs 66 b, 66 c and the underlying insulating layer 63 b.

[0219] The Ir layer 18 of 200 nm thickness is formed by the sputtermethod under the conditions that, for example, the substrate temperatureis set to 400° C., the power is set to 1 kW, the argon (Ar) gas isintroduced into the growth atmosphere at the flow rate of 100 sccm, andthe growth time is set to 144 seconds.

[0220] The IrO_(x) layer 20 of 28 nm thickness is formed by the sputtermethod under the conditions that, for example, the substrate temperatureis set to 400° C., the power is set to 1 kW, the argon (Ar) gas isintroduced into the growth atmosphere at the flow rate of 60 sccm, theoxygen (O₂) gas is introduced into the growth atmosphere at the flowrate of 20 sccm, and the growth time is set to 10 seconds. According tosuch conditions, the composition ratio x of the oxygen (O) in theIrO_(x) layer 20 is x=1 to 1.2 to provide the metallic structure.

[0221] Then, as shown in FIG. 19E, the first platinum (Pt) layer 21, theplatinum oxide (PtO_(x)) layer 22, and the second platinum (Pt) layer 24are formed in sequence on the IrO_(x) layer 20.

[0222] The first Pt layer 21 is the Pt-interface layer to control thecrystal orientation of the platinum oxide (PtO_(x)) layer 22. Forexample, the first Pt layer 21 of 5 nm thickness is formed by thesputter method under the conditions that, for example, the substratetemperature is set to 350° C., the power is set to 1 kW, the Ar gas isintroduced into the growth atmosphere at the flow rate of 100 sccm, andthe growth time is set to 4 seconds.

[0223] The PtO_(x) layer 22 of 30 nm thickness is formed by the sputtermethod under the conditions that, for example, the substrate temperatureis set to 350° C., the power is set to 1 kW, the Ar gas is introducedinto the growth atmosphere at the flow rate of 36 sccm, the oxygen (O₂)gas is introduced into the growth atmosphere at the flow rate of 144sccm, and the growth time is set to 27 seconds.

[0224] The second Pt layer 24 of 50 nm thickness is formed by thesputter method under the conditions that, for example, the substratetemperature is set to 100° C., the power is set to 1 kW, the Ar gas isintroduced into the growth atmosphere at the flow rate of 100 sccm, andthe growth time is set to 34 seconds.

[0225] In this case, it is preferable that the first Pt layer 21, thePtO_(x) layer 22, and the second Pt layer 24 should be formedsuccessively by the same sputter equipment.

[0226] Then, the second Pt layer 24 is crystallized by executing therapid thermal annealing process for 60 seconds at 750° C. in theargon-introduced atmosphere.

[0227] The Pt/PtO_(x)/Pt/IrO_(x)/Ir structure consisting of the Ir layer18, the IrO_(x) layer 20, the first Pt layer 21, the PtO_(x) layer 22,and the second Pt layer 24, as described above, is used as the lowerelectrode conductive layer 17.

[0228] Then, as shown in FIG. 19F, the PZT layer of 100 nm thickness,for example, is formed on the lower electrode conductive layer 17 as theferroelectric layer 26 by the sputter method. As the material of theferroelectric layer 26, in addition to PZT, other PZT-based materialsuch as PLCSZT, PLZT, etc., the Bi layer structure compound materialsuch as SBT (SrBi₂Ta₂O₉), SrBi₂(Ta, Nb)₂O₉, etc., and other metal oxideferroelectric substance may be employed. Also, if the high-dielectriccapacitor is to be formed, the high-dielectric layer such asBa_(x)Sr_(1-x)TiO₃, SrTiO₃, PLZT, etc. is formed in place of theferroelectric layer.

[0229] Then, the ferroelectric layer 26 is crystallized by executing theannealing in the oxygen atmosphere. As the annealing, for example,two-step rapid thermal annealing (RTA) process that comprises theannealing executed for a time of 90 seconds at the substrate temperatureof 600° C. in the mixed gas atmosphere of argon and oxygen as the firststep, and the annealing executed for a time of 60 seconds at thesubstrate temperature of 750° C. in the oxygen atmosphere as the secondstep.

[0230] Also, the iridium oxide (IrO_(x)) of 200 nm thickness, forexample, is formed as the upper electrode conductive layer 27 on theferroelectric layer 26 by the sputter method. In this case, the Pt layermay be formed as the upper electrode conductive layer 27 in place of theIrO_(x) layer.

[0231] After this, the TiN layer and the SiO₂ layer are formedsequentially on the upper electrode conductive layer 27 as a hard mask(not shown). This hard mask is patterned by the photolithography methodto form the planar shape of the capacitor over the second and thirdconductive plugs 66 b, 66 c.

[0232] Then, as shown in FIG. 19G, the upper electrode conductive layer27, the ferroelectric layer 26, and the lower electrode conductive layer17 located in the region not covered with the hard mask (not shown) areetched sequentially.

[0233] As a result, the lower electrode 30 a made of the lower electrodeconductive layer 17, the dielectric layer 32 a made of the ferroelectriclayer 26, and the upper electrode 34 a made of the upper electrodeconductive layer 27 are formed on the underlying insulating layer 63 b.Thus, the capacitor Q is formed by the upper electrode 34 a, theferroelectric layer 26, and the lower electrode 30 a.

[0234] Then, in the transistor forming region, one lower electrode 30 ais connected electrically to the second impurity diffusion region 56 bvia the second conductive plug 66 b, and also the other lower electrode30 a is connected electrically to the third impurity diffusion region 56c via the third conductive plug 66 c.

[0235] After this, the hard mask (not shown) is removed.

[0236] Then, in order to recover the damage of the ferroelectric layer26 due to the etching, the recovery annealing is carried out. In thiscase, the recovery annealing is carried out at the substrate temperatureof 650° C. for 60 minutes in the oxygen atmosphere, for example.

[0237] Then, as shown in FIG. 19H, alumina of 50 nm thickness is formedon the substrate by the sputter as the protection layer 86 that coversthe capacitor Q. Then, the capacitor Q is annealed at 650° C. for 60minutes in the oxygen atmosphere. This protection layer 86 protects thecapacitor Q from the process damage, and may be formed of PZT.

[0238] Then, silicon oxide (SiO₂) of about 1.0 μm thickness is formed asthe second interlayer insulating layer 88 on the protection layer 86 bythe plasma CVD method using the TEOS gas. In addition, the upper surface of the second interlayer insulating layer 88 is planarized by theCMP method.

[0239] Next, steps required until the structure shown in FIG. 19I isformed will be explained hereunder.

[0240] First, the hole 90 is formed on the first conductive plug 66 a byetching selectively the second interlayer insulating layer 88, theprotection layer 86, the oxidation preventing insulating layer 63 a, andthe underlying insulating layer 63 b while using the resist mask (notshown). After this etching, in order to recover the ferroelectric layer26 constituting the dielectric layer 32 a of the capacitor Q from thedamage, the annealing is applied at the substrate temperature of 550° C.for 60 minutes in the oxygen atmosphere, for example.

[0241] Then, the TiN layer of 50 nm thickness is formed as the gluelayer in the hole 90 and on the second interlayer insulating layer 88 bythe sputter method. Then, the W layer is grown on the glue layer by theCVD method and is filled perfectly in the hole 90.

[0242] Then, the W layer and the TiN layer are removed from the uppersurface of the second interlayer insulating layer 88 by polishing themby the CMP method. Then, the tungsten layer and the glue layer left inthe hole 90 are used as the fourth conductive plug 92. This fourthconductive plug 92 is connected electrically to the first impuritydiffusion region 56 a via the first conductive plug 66 a.

[0243] Next, steps required until the structure shown in FIG. 19J isformed will be explained hereunder.

[0244] First, the SiON layer is formed as the second oxidationpreventing layer 89 on the fourth conductive plug 92 and the secondinterlayer insulating layer 88 by the CVD method. Then, the contactholes 94 are formed on the upper electrodes 34 a of the capacitors Q bypatterning the second oxidation preventing layer 89 and the secondinterlayer insulating layer 88 by virtue of the photolithography method.

[0245] The capacitors Q that are damaged by the formation of the contactholes 94 are recovered by the annealing. This annealing is carried outat the substrate temperature of 550° C. for 60 minutes in the oxygenatmosphere, for example.

[0246] Then, the second oxidation preventing layer 89 formed on thesecond interlayer insulating layer 88 is removed by the etching-back andthe upper surface of the fourth conductive plug 92 is exposed.

[0247] Next, steps required until the sectional structure shown in FIG.19K is obtain will be explained as follows. A multi-layered metal layeris formed in the contact holes 94 on the upper electrodes 34 a of thecapacitors Q and on the second interlayer insulating layer 88. Then, thewiring layers 98 made of the multi-layered metal layer, which areconnected to the upper electrodes 34 a via the contact holes 94, and theconductive pad 99 made of the multi-layered metal layer, which isconnected to the fourth conductive plug 92, are formed by patterning themulti-layered metal layer. As the multi-layered metal layer, forexample, Ti of 60 nm thickness, TiN of 30 nm thickness, Al—Cu of 400 nmthickness, Ti of 5 nm thickness, and TiN of 70 nm thickness are formedin sequence.

[0248] Then, as the method of patterning the multi-layered metal layer,the method of forming the reflection preventing layer on themulti-layered metal layer, then coating the resist on the reflectionpreventing layer, then exposing/developing the resist to form the resistpatterns of the wiring shape, etc., and then executing the etching byusing the resist pattern is employed.

[0249] In addition, a third interlayer insulating layer 97 is formed onthe second interlayer insulating layer 88, the wiring layers 98, and theconductive pad 99. Then, a hole 97 a is formed on the conductive pad 99by patterning the third interlayer insulating layer 97. Then, a fifthconductive plug 95 consisting of the Ti layer and the W layersequentially from the bottom is formed in the hole 97 a.

[0250] Then, although not particularly shown, the second wiringcontaining the bit line is formed on the third interlayer insulatinglayer 97. The bit line is connected electrically to the first impuritydiffusion region 56 a via the fifth conductive plug 95, the conductivepad 99, the fourth conductive plug 92, and the first conductive plug 66a. Subsequently, the insulating layer for covering the second wiringlayer, etc. are formed, but their details are omitted.

[0251] The above steps are steps of forming the FeRAM memory cellregion.

[0252] The capacitor Q formed by above steps has the lower electrode 30a having the Pt/PtO_(x)/Pt/IrO_(x)/Ir structure. Thus, like the fourthembodiment, the (111) orientation of the uppermost Pt layer 24 in thelower electrode 30 a is enhanced and thus the PZT layer 26 formedthereon or other oxide dielectric layer is easily oriented in the (111)direction, so that the layer quality can be improved.

[0253] Therefore, like the first embodiment, effects such as thereduction in the leakage current of the capacitor Q and the oxidationprevention of the conductive plugs 66 b, 66 c immediately under thecapacitor Q can be achieved. In addition, the polarization saturationvoltage of the capacitor Q can be reduced rather than the capacitor inthe first embodiment, the switching electric charge amount of thecapacitor Q can be increased rather than the capacitor in the firstembodiment, the fatigue loss of the capacitor Q can be reduced ratherthan the capacitor in the first embodiment, and the retentioncharacteristic can be increased rather than the capacitor in the firstembodiment.

[0254] In this case, as the capacitor Q constituting the memory cell,the structure shown in FIG. 18 may be employed.

[0255] As described in detail, features of the capacitor and the methodof manufacturing the same and the semiconductor device according to thepresent invention are summarized as follows.

[0256] As described, according to the present invention, the capacitoris constructed by the lower electrode having the first conductive layerin which the iridium is contained, the second conductive layer which isformed on the first conductive layer and made of the platinum groupmetal oxide except the iridium, and the third conductive layer which isformed on the second conductive layer and made of the platinum groupmetal except the iridium, the capacitor dielectric layer formed on thelower electrode, and the upper electrode formed on the capacitordielectric layer. Therefore, the diffusion of the oxygen into theunderlying plug in the course of the layer formation of the capacitordielectric layer can be prevented by the first conductive layer, andalso the diffusion of the iridium from the first conductive layer to thecapacitor dielectric layer can be prevented by the second conductivelayer.

[0257] Therefore, even if the capacitor dielectric layer is formed bythe sputtering, the sufficient crystallization of the capacitordielectric layer can be achieved while preventing the diffusion of theiridium. As a result, the high performance capacitor having the desiredelectric characteristics can be manufactured.

[0258] In addition, according to the present invention, the interfaceconductive layer made of the platinum group metal except the iridium,e.g., the platinum, is formed between the first conductive layer and thesecond conductive layer. Therefore, the (111) integrated intensities ofthe third conductive layer and the overlying ferroelectric layer can beenhanced and thus the electric characteristics of the ferroelectriccapacitor can be improved.

What is claimed is:
 1. A capacitor comprising: a lower electrode havinga structure in which a first conductive layer containing a first metal,a second conductive layer that is formed on the first conductive layerand made of a metal oxide of a second metal different from the firstmetal, and a third conductive layer that is formed on the secondconductive layer and made of a third metal different from the firstmetal are formed sequentially on an insulating layer; a dielectric layerformed on the lower electrode; and an upper electrode formed on thecapacitor dielectric layer.
 2. A capacitor according to claim 1, whereinthe first metal is iridium, the metal oxide of the second metal is ametal oxide of a platinum group metal except the iridium, and the thirdmetal is the platinum group metal except the iridium.
 3. A capacitoraccording to claim 1, wherein the second metal is a same element as thethird metal, and an interface conductive layer made of the second metalis further formed between the first conductive layer and the secondconductive layer.
 4. A capacitor according to claim 3, wherein thesecond metal is platinum.
 5. A capacitor according to claim 1, whereinthe first conductive layer contains iridium or ruthenium and has afunction for preventing diffusion of oxygen, and the second conductivelayer has a function for preventing diffusion of the iridium or theruthenium.
 6. A capacitor according to claim 1, wherein the second metalis platinum, and the second conductive layer is a platinum oxide layer.7. A capacitor according to claim 1, wherein the third metal isplatinum, and the third conductive layer is a platinum layer.
 8. Acapacitor according to claim 1, wherein the first conductive layer is astacked layer in which a first metal layer and a first metal oxide layerare formed sequentially.
 9. A capacitor according to claim 8, whereinthe first metal layer is an iridium layer and the first metal oxidelayer is an iridium oxide layer.
 10. A capacitor according to claim 9,wherein an iridium oxide is represented by IrO_(x)(0<x<1.2).
 11. Acapacitor according to claim 1, wherein the dielectric layer is any oneof a ferroelectric layer and a high-dielectric layer.
 12. A capacitoraccording to claim 1, further comprising a substrate, an insulatinglayer formed above the substrate, and an electrode plug buried in theinsulating layer, and wherein the lower electrode is formed on theelectrode plug.
 13. A manufacturing method of a capacitor comprising thesteps of: forming a first conductive layer containing a first metal onan insulating layer; forming a second conductive layer made of a metaloxide of a second metal, that is different from the first metal, on thefirst conductive layer; forming a third conductive layer made of a thirdmetal, that is different from the first metal, on the second conductivelayer; forming a dielectric layer on the third conductive layer; forminga fourth conductive layer on the dielectric layer; patterning the fourthconductive layer to form a capacitor upper electrode; patterning thedielectric layer to form a capacitor dielectric layer; and patterningthe first conductive layer, the second conductive layer, and the thirdconductive layer to form a capacitor lower electrode.
 14. Amanufacturing method of a capacitor according to claim 13, wherein anelement of the first metal is iridium, a metal oxide of the second metalis a metal oxide of a platinum group, that is different from theiridium, and the third metal is a metal of the platinum group, that isdifferent from the iridium.
 15. A manufacturing method of a capacitoraccording to claim 13, wherein the second metal is a same element as thethird metal, and further comprising the step of forming an interfaceconductive layer made of the second metal between the first conductivelayer and the second conductive layer.
 16. A manufacturing method of acapacitor according to claim 13, wherein formation of the firstconductive layer contains the step of forming the first metal layer andthe first metal oxide layer sequentially.
 17. A manufacturing method ofa capacitor according to claim 16, wherein the first metal layer is aniridium layer, and the first metal oxide layer is iridium oxide, and theiridium oxide is formed by adjusting an oxygen gas and an inert gas in agrowth atmosphere to attain IrO_(x) (0<x<1.2).
 18. A manufacturingmethod of a capacitor according to claim 13, wherein, in the step offorming the second conductive layer, the second conductive layer made ofplatinum oxide is formed at a temperature of more than 200° C. and lessthan 400° C.
 19. A manufacturing method of a capacitor according toclaim 13, wherein, in the step of forming the third conductive layer,the third conductive layer made of platinum is formed at a temperatureof less than 400° C.
 20. A semiconductor device comprising: a transistorformed on a semiconductor substrate, and having a gate electrode andsource/drain diffusion layers formed in the semiconductor substrate onboth sides of the gate electrode; an insulating layer for covering thetransistor; an electrode plug buried in the insulating layer andconnected electrically to the source/drain diffusion layer; and acapacitor formed on the electrode plug, and having a lower electrodethat has a first conductive layer containing iridium, a secondconductive layer formed on the first conductive layer and made of ametal oxide of a platinum group except the iridium and a thirdconductive layer formed on the second conductive layer and made of ametal of the platinum group except the iridium, a capacitor dielectriclayer that is formed on the lower electrode by sputtering, and an upperelectrode that is formed on the capacitor dielectric layer, and thelower electrode is connected electrically to the electrode plug.
 21. Asemiconductor device according to claim 20, wherein the secondconductive layer is a platinum oxide layer.
 22. A semiconductor deviceaccording to claim 20, wherein the third conductive layer is a platinumlayer.
 23. A semiconductor device according to claim 20, wherein thefirst conductive layer is a stacked layer consisting of an iridium layerand an iridium oxide layer formed on the iridium layer.
 24. Asemiconductor device according to claim 20, wherein an interfaceconductive layer made of a metal of a platinum group, that is differentfrom the iridium, is formed between the first conductive layer and thesecond conductive layer.
 25. A semiconductor device according to claim24, wherein the interface conductive layer is platinum.
 26. Asemiconductor device comprising: a transistor formed on a semiconductorsubstrate, and having a gate electrode and source/drain diffusion layersformed in the semiconductor substrate on both sides of the gateelectrode; an insulating layer for covering the transistor; an electrodeplug buried in the insulating layer and connected electrically to thesource/drain diffusion layer; and a capacitor formed on the electrodeplug, and having a lower electrode that has a first conductive layercontaining iridium and for preventing diffusion of oxygen, a secondconductive layer formed on the first conductive layer and for preventingdiffusion of the iridium from the first conductive layer and a thirdconductive layer formed on the second conductive layer and made of ametal of a platinum group except the iridium, a capacitor dielectriclayer that is formed on the lower electrode by sputtering, and an upperelectrode that is formed on the capacitor dielectric layer, and thelower electrode is connected electrically to the electrode plug.
 27. Asemiconductor device according to claim 26, wherein the secondconductive layer is a platinum oxide layer.
 28. A semiconductor deviceaccording to claim 26, wherein the third conductive layer is a platinumlayer.
 29. A semiconductor device according to claim 26, wherein thefirst conductive layer is a stacked layer consisting of an iridium layerand an iridium oxide layer formed on the iridium layer.
 30. Asemiconductor device according to claim 26, wherein an interfaceconductive layer made of a metal of a platinum group, that is differentfrom the iridium, is formed between the first conductive layer and thesecond conductive layer.
 31. A semiconductor device according to claim30, wherein the interface conductive layer is platinum.